Semiconductor integrated circuits utilizing high impedance transistor technologies such as metal oxide semiconductor (MOS) technologies are known to be vulnerable to ESD. ESD “events” may include the so-called “human body model” (HBM) type of event. See e.g., JEDEC Standard JS-001-2012, JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST-HUMAN BODY MODEL (HBM)-COMPONENT LEVEL (2012) for additional information about HBM. A person may accumulate static electrical charge on the surface of his or her body, generally through the rubbing together of dissimilar articles of clothing, shoes rubbing against carpet, clothing rubbing against a car seat when entering or exiting a vehicle, etc., particularly at times of low relative humidity. An HBM ESD event occurs when the person subsequently touches a conductor, including perhaps an electronic circuit and discharges the accumulated charge to and through circuit components. Such components may be subject to damage by a resulting discharge pulse of 1000 volts or more with a discharge time of several hundred nanoseconds.
In an integrated circuit, different chip applications may require different levels of ESD protection for ensuring adequate reliability through the manufacturing process. ESD protection devices utilizing a metal oxide semiconductor field-effect transistor (MOSFET) as a discharge device between voltage rails are known. A MOSFET designed for such purpose typically includes a wide, short current channel that is able to conduct several amperes of current produced by a typical ESD event. The transistors (also known as clamps) are triggered with an ESD transient and shunt the ESD current between the power rails. The current handling capability of the MOSFET should be changed to handle the currents associated with different ESD levels. These MOSFETs can be sized to handle the expected ESD current. Less current allows the clamp width to be reduced. The general practice is to design a single ESD solution for the highest level of ESD protection required, but this means that applications with less stringent requirements have inefficient use of layout area. Thus, it is desirable to have an ESD protection apparatus that caters to varying levels of ESD protection.